Fujitsu Reveals Monaka CPU with Separate Cache Die and 256-bit SVE2

Monaka CPU Architecture Overview

At the Hot Chips 2026 conference on August 24, Fujitsu unveiled its next‑generation server processor, code‑named Monaka. The chip packs 144 Arm cores, each based on the latest A78 design, and targets high‑performance computing (HPC) and artificial intelligence workloads. The announcement confirmed that Monaka moves away from the 512‑bit SVE implementation used in the A64FX, opting instead for two independent 256‑bit SVE2 vector units per core.

Core count and clocking strategy

Monaka is built on a 7nm process for the compute die, while the cache subsystem resides on a dedicated 5nm die. Fujitsu plans to offer two power‑tiered SKUs: a 350‑watt version for dense HPC clusters and a 500‑watt version for peak performance machines. Both variants are expected to ship in early 2027.

Separate Cache Die on a 5nm Process

One of the most striking design choices is the decision to place the entire cache hierarchy on a separate 5nm chip. This approach mirrors the chip‑on‑chip (CoC) strategy employed by some GPU manufacturers, but it is rare for a CPU that targets the server market.

• Cache capacity: 64 MB of L2 cache per core, aggregated across the cache die.
• Inter‑die bandwidth: Fujitsu cites a proprietary silicon‑photonic link that delivers up to 1 TB/s of data transfer between the compute and cache dies.
• Power efficiency: By moving the cache to a smaller node, static power leakage is reduced, contributing to the 350 W power envelope.

The separation also allows Fujitsu to upgrade the cache die independently in future revisions, potentially adding larger L3 or L4 caches without redesigning the main compute core.

Vector Units and SVE2 Width

Monaka’s dual 256‑bit SVE2 units represent a deliberate trade‑off. While the A64FX’s 512‑bit SVE offered higher raw vector throughput, the narrower units simplify hardware design and reduce power draw. Each core can issue two vector instructions per cycle, effectively matching the instruction‑level parallelism of the older design.

Arm’s Scalable Vector Extension version 2 (SVE2) adds support for complex integer arithmetic, widening the processor’s appeal to machine‑learning inference workloads that rely heavily on matrix operations. The 256‑bit width aligns with the emerging trend of using mixed‑precision formats such as BF16 and FP16, which fit comfortably within the vector lanes.

Key vector specifications

1. Two 256‑bit vector pipelines per core.
2. Support for FP64, FP32, BF16, FP16, and integer types up to 64 bits.
3. Hardware‑accelerated dot‑product instructions for AI kernels.
4. Full compatibility with Arm’s SVE2 software ecosystem, including compilers and libraries.

Power Targets and SKU Options

The two SKUs address distinct market segments. The 350 W model is aimed at hyperscale data centers where power density is a primary concern. The 500 W model, by contrast, targets flagship supercomputers that prioritize raw performance over power constraints.

Both versions share the same core count and cache architecture; the difference lies in clock frequency and voltage scaling. Fujitsu reports the 350 W SKU will run at a base frequency of 2.2 GHz, while the 500 W SKU can boost to 2.8 GHz under load.

Implications for Data Center Workloads

Monaka’s architecture is tailored for workloads that benefit from massive parallelism and high memory bandwidth. Typical use cases include:

• Scientific simulations that rely on double‑precision floating‑point calculations.
• AI training pipelines that can exploit mixed‑precision matrix multiplications.
• Real‑time data analytics where low latency is critical.

By separating the cache die, Fujitsu reduces the thermal envelope of the compute die, potentially allowing tighter rack designs. The dual 256‑bit SVE2 units also simplify compiler optimizations, as existing software tuned for 256‑bit vectors can be ported with minimal changes.

Comparison with A64FX and Competitors

Fujitsu’s previous flagship, the A64FX, set a benchmark for ARM‑based HPC with its 48‑core layout and 512‑bit SVE. Monaka doubles the core count and introduces a modular cache solution. Compared with Intel’s Sapphire Rapids and AMD’s Genoa processors, Monaka offers a unique blend of high core density and ARM’s energy‑efficient instruction set.

Key differentiators include:

• Separate cache die on a leading‑edge 5nm node.
• Dual 256‑bit SVE2 pipelines per core, providing flexibility for AI and HPC.
• Targeted power envelopes that align with both hyperscale and exascale markets.

Benchmark expectations

Early simulations suggest Monaka could achieve up to 3.5 TFLOPS per watt on mixed‑precision AI kernels, a figure that would place it ahead of many current x86 server CPUs. Real‑world performance will depend on software stacks that can fully leverage the SVE2 extensions.

Roadmap and Market Expectations

Fujitsu plans to begin silicon validation in late 2026, with volume production scheduled for early 2027. The company has hinted at future iterations that may expand the cache die to include high‑bandwidth memory (HBM) stacks, further boosting memory throughput for data‑intensive tasks.

Industry analysts expect the Monaka launch to reinforce Fujitsu’s position in the niche but growing ARM‑based server market. The combination of a modular cache architecture and a balanced vector width could attract customers seeking a middle ground between power efficiency and raw performance.

For more details on Fujitsu’s announcement, see the Fujitsu press release. Technical information on Arm’s SVE2 can be found in the Arm SVE documentation. The Hot Chips conference website provides additional context on the event where Monaka was introduced: Hot Chips 2026. Analysis of the competitive landscape is available from The Register.