OpenAI Deploys Jalapeño ASICs with AMD EPYC Turin CPUs Over Nvidia Vera

Why OpenAI chose AMD EPYC Turin CPUs

OpenAI’s latest data centre design relies on a combination of its own Jalapeño ASICs and AMD EPYC Turin CPUs. The decision reflects a focus on proven performance, flexible memory architecture and a roadmap that aligns with the company’s scaling ambitions.

AMD EPYC Turin processors offer a high core count, large cache and support for the latest DDR5 and PCIe 5.0 standards. Those features enable the Jalapeño ASICs to receive data quickly and to feed results back to the host without bottlenecks.

Up to 96 cores per socket provide ample parallelism for orchestration tasks.
Integrated Infinity Fabric improves communication between CPU and accelerator.
Broad software ecosystem reduces integration risk.

OpenAI announced the partnership in a hardware briefing that highlighted the synergy between the two silicon families. The company cited lower latency, higher throughput and a clear upgrade path as primary reasons for the selection.OpenAI hardware briefing

Jalapeño ASIC architecture

The Jalapeño ASIC is a custom accelerator built to handle the most demanding inference and training workloads. Its design emphasizes dense matrix multiplication, low‑power operation and tight integration with the host CPU.

Design goals

OpenAI set three core goals for Jalapeño:

Maximize operations per watt for large language models.
Provide a programmable interface that supports future model variants.
Maintain a form factor that fits within standard rack units.

Performance metrics

Benchmarks released by OpenAI show that a single Jalapeño chip can deliver over 200 teraflops of mixed‑precision compute while staying under 250 watts of power draw. When paired with an AMD EPYC Turin socket, the system reaches a combined throughput that surpasses many traditional GPU clusters.

Key performance figures include:

Peak mixed‑precision throughput: 200+ teraflops.
Power efficiency: roughly 0.8 teraflops per watt.
Memory bandwidth: 2.5 terabytes per second via HBM2e.

Comparison with Nvidia Vera

Nvidia’s Vera chip has generated excitement as a next‑generation agentic accelerator. However, OpenAI opted not to adopt Vera for its current rack deployments. The reasons are largely strategic and technical.

Vera relies on a newer interconnect that is not yet widely supported in existing data centre fabrics.
Software stacks for Vera are still in early beta, increasing integration risk.
Cost per unit remains higher than the combined price of Jalapeño plus EPYC Turin.

For a detailed overview of Vera, see the official Nvidia product page.Nvidia Vera chip

Implications for data centre strategy

Choosing Jalapeño and EPYC Turin shapes OpenAI’s broader infrastructure approach. The combination supports a modular, rack scale architecture that can be expanded incrementally.

Scalability

Each rack can host multiple EPYC Turin sockets, each attached to several Jalapeño boards. This layout allows OpenAI to scale compute capacity linearly, matching demand without a complete redesign.

Cost efficiency

By avoiding the premium pricing of newer agentic chips, OpenAI reduces capital expenditure while still achieving high performance. The use of widely available EPYC processors also simplifies procurement and maintenance.

Lower total cost of ownership compared with GPU‑heavy solutions.
Reduced need for specialized cooling due to efficient power usage.
Simplified supply chain thanks to AMD’s established manufacturing network.

Future outlook for custom silicon in advanced workloads

OpenAI’s hardware choices illustrate a broader industry trend toward custom silicon that works hand‑in‑hand with general‑purpose CPUs. While chips like Arm’s AGI accelerator are on the horizon, the immediate focus remains on solutions that offer mature software support and predictable performance.

Arm’s roadmap for AGI‑class processors highlights ambitious goals, but adoption timelines suggest they will complement rather than replace existing designs in the near term.Arm AGI chip roadmap

Analysts predict that the next wave of data centre hardware will feature heterogeneous mixes of CPUs, custom ASICs and GPUs, each selected for the specific workload they accelerate best. OpenAI’s deployment of Jalapeño ASICs alongside AMD EPYC Turin CPUs positions the company to benefit from that mixed‑architecture future while keeping operational risk low.

As the ecosystem evolves, the balance between performance, power efficiency and cost will continue to guide hardware decisions across the AI research community.